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| d a t a sh eet product speci?cation supersedes data of 1997 mar 19 file under integrated circuits, ic12 1997 oct 21 integrated circuits PCF8584 i 2 c-bus controller
1997 oct 21 2 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 contents 1 features 2 general description 3 ordering information 4 block diagram 5 pinning 6 functional description 6.1 general 6.2 interface mode control (imc) 6.3 set-up registers s0', s2 and s3 6.4 own address register s0' 6.5 clock register s2 6.6 interrupt vector s3 6.7 data shift register/read buffer s0 6.8 control/status register s1 6.8.1 register s1 control section 6.8.1.1 pin (pending interrupt not) 6.8.1.2 eso (enable serial output) 6.8.1.3 es1 and es2 6.8.1.4 eni 6.8.1.5 sta and sto 6.8.1.6 ack 6.8.2 register s1 status section 6.8.2.1 pin bit 6.8.2.2 sts 6.8.2.3 ber 6.8.2.4 lrb/ad0 6.8.2.5 aas 6.8.2.6 lab 6.8.2.7 bb 6.9 multi-master operation 6.10 reset 6.11 comparison to the mab8400 i 2 c-bus interface 6.11.1 deleted functions 6.11.2 added functions 6.12 special function modes 6.12.1 strobe 6.12.2 long-distance mode 6.12.3 monitor mode 7 software flowchart examples 7.1 initialization 7.2 implementation 8i 2 c-bus timing diagrams 9 limiting values 10 handling 11 dc characteristics 12 i 2 c-bus timing specifications 13 parallel interface timing 14 application information 14.1 application notes 15 package outlines 16 soldering 16.1 introduction 16.2 dip 16.2.1 soldering by dipping or by wave 16.2.2 repairing soldered joints 16.3 so 16.3.1 reflow soldering 16.3.2 wave soldering 16.3.3 repairing soldered joints 17 definitions 18 life support applications 19 purchase of philips i 2 c components 1997 oct 21 3 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 1 features parallel-bus to i 2 c-bus protocol converter and interface compatible with most parallel-bus microcontrollers/microprocessors including 8049, 8051, 6800, 68000 and z80 both master and slave functions automatic detection and adaption to bus interface type programmable interrupt vector multi-master capability i 2 c-bus monitor mode long-distance mode (4-wire) operating supply voltage 4.5 to 5.5 v operating temperature range: - 40 to +85 c. 2 general description the PCF8584 is an integrated circuit designed in cmos technology which serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial i 2 c-bus. the PCF8584 provides both master and slave functions. communication with the i 2 c-bus is carried out on a byte-wise basis using interrupt or polled handshake. it controls all the i 2 c-bus specific sequences, protocol, arbitration and timing. the PCF8584 allows parallel-bus systems to communicate bidirectionally with the i 2 c-bus. 3 ordering information type number package name description version PCF8584p dip20 plastic dual in-line package; 20 leads (300 mil) sot146-1 PCF8584t so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 1997 oct 21 4 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 4 block diagram fig.1 block diagram. (1) x = dont care. (2) pin mnemonics between parenthesis indicate the 68000 mode pin designations. (3) these pin mnemonics represent the long-distance mode pin designations. handbook, full pagewidth mbd908 - 1 db6 db7 db5 db4 db3 db2 db1 db0 14 15 13 12 11 9 8 7 read buffer shift register data shift register s0 and read buffer write only 8 msb msb lsb comparator s0, s0' own address s0' x 8 interrupt vector s3 8 clock register s2 8 s20 s21 s22 s23 s24 0 0 0 clock register s2 8 ack sto sta eni es2 es1 es0 pin register s1 control status bb lab aas ad0/ lrb ber sts 0 pin write only read only register access control bus buffer control interrupt control reset/strobe control int scl out iack sda in clk 541 vv dd ss 20 10 data control digital filter sda/ sda out 2 scl control digital filter scl/ scl in 3 PCF8584 reset/ cs a0 19 17 6 strobe (o.c.) wr (r/w) 18 rd (dtack) 16 clock prescaler scl multiplexer bus busy logic arbitration logic x parallel bus control status register s1 read only (1) (1) (3) (3) (2) (2) (3) (3) parallel bus control default: 00h 80xx 0fh 68xxx 1997 oct 21 5 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 5 pinning symbol pin i/o description clk 1 i clock input from microcontroller clock generator (internal pull-up) sda or sda out 2 i/o i 2 c-bus serial data input/output (open-drain). serial data output in long-distance mode. scl or scl in 3 i/o i 2 c-serial clock input/output (open-drain). serial clock input in long-distance mode. iack or sda in 4 i interrupt acknowledge input (internal pull-up); when this signal is asserted the interrupt vector in register s3 will be available at the bus port if the eni ?ag is set. serial data input in long-distance mode. int or scl out 5 o interrupt output (open-drain); this signal is enabled by the eni ?ag in register s1. it is asserted when the pin ?ag is reset. (pin is reset after 1 byte is transmitted or received over the i 2 c-bus). serial clock output in long-distance mode. a0 6 i register select input (internal pull-up); this input selects between the control/status register and the other registers. logic 1 selects register s1, logic 0 selects one of the other registers depending on bits loaded in eso, es1 and es2 of register s1. db0 7 i/o bidirectional 8-bit bus port 0 db1 8 i/o bidirectional 8-bit bus port 1 db2 9 i/o bidirectional 8-bit bus port 2 v ss 10 - ground db3 11 i/o bidirectional 8-bit bus port 3 db4 12 i/o bidirectional 8-bit bus port 4 db5 13 i/o bidirectional 8-bit bus port 5 db6 14 i/o bidirectional 8-bit bus port 6 db7 15 i/o bidirectional 8-bit bus port 7 rd ( dt ack) 16 i/(o) rd is the read control input for mab8049, mab8051 or z80-types. dt ack is the data transfer control output for 68000-types (open-drain). cs 17 i chip select input (internal pull-up) wr (r/ w) 18 i wr is the write control input for mab8048, mab8051, or z80-types (internal pull-up). r/ w control input for 68000-types. reset/ strobe 19 i/o reset input (open-drain); this input forces the i 2 c-bus controller into a prede?ned state; all ?ags are reset, except pin, which is set. also functions as strobe output. v dd 20 - supply voltage 1997 oct 21 6 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 6 functional description 6.1 general the PCF8584 acts as an interface device between standard high-speed parallel buses and the serial i 2 c-bus. on the i 2 c-bus, it can act either as master or slave. bidirectional data transfer between the i 2 c-bus and the parallel-bus microcontroller is carried out on a byte-wise basis, using either an interrupt or polled handshake. interface to either 80xx-type (e.g. 8048, 8051, z80) or 68000-type buses is possible. selection of bus type is automatically performed (see section 6.2). fig.2 pin configuration. handbook, halfpage clk sda or sda out scl or scl in a0 db0 db1 db2 v ss v dd db7 db6 db5 db4 db3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PCF8584 mla012 - 1 iack or sda in int or scl out reset / strobe cs rd (dtack) wr (r/w) (1) (1) (1) pin mnemonics between parenthesis indicate the 68000 mode pin designations. table 1 control signals utilized by the PCF8584 for microcontroller/microprocessor interfacing the structure of the PCF8584 is similar to that of the i 2 c-bus interface section of the philips mabxxxx/pcf84(c)xx-series of microcontrollers, but with a modified control structure. the PCF8584 has five internal register locations. three of these (own address register s0', clock register s2 and interrupt vector s3) are used for initialization of the PCF8584. normally they are only written once directly after resetting of the PCF8584. the remaining two registers function as double registers (data buffer/shift register s0, and control/status register s1) which are used during actual data transmission/reception. by using these double registers, which are separately write and read accessible, overhead for register access is reduced. register s0 is a combination of a shift register and data buffer. register s0 performs all serial-to-parallel interfacing with the i 2 c-bus. register s1 contains i 2 c-bus status information required for bus access and/or monitoring. 6.2 interface mode control (imc) selection of either an 80xx mode or 68000 mode interface is achieved by detection of the first wr- cs signal sequence. the concept takes advantage of the fact that the write control input is common for both types of interfaces. an 80xx-type interface is default. if a high-to-low transition of wr (r/ w) is detected while cs is high, the 68000-type interface mode is selected and the dtack output is enabled. care must be taken that wr and cs are stable after reset. type r/ w wr r dt ack iack 8048/ 8051 no yes yes no no 68000 yes no no yes yes z80 no yes yes no yes 1997 oct 21 7 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.3 68000/80xx timing sequence utilized by the interface mode control (imc). handbook, full pagewidth filter t = 16clk reset strobe d en d en enrd sio divider (s21 and s20) divider (s24, s23, s22) /2, 3, 4, 5, 8 i 2 c-bus (1.5 mhz) cs a0 scl int iack clk (50 : 50) wr/ r/w rd/ dtack mbe706 handbook, full pagewidth mode select mode locked r/w cs dtack mode select wr cs mbe707 (1) (2) (1) bus timing; 68000 mode write cycle. (2) bus timing; 80xx mode. 1997 oct 21 8 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 6.3 set-up registers s0', s2 and s3 registers s0', s2 and s3 are used for initialization of the PCF8584 (see fig.5 initialization sequence flowchart). 6.4 own address register s0' when the PCF8584 is addressed as slave, this register must be loaded with the 7-bit i 2 c-bus address to which the PCF8584 is to respond. during initialization, the own address register s0' must be written to, regardless whether it is later used. the addressed as slave (aas) bit in status register s1 is set when this address is received (the value in s0 is compared with the value in s0'). note that the s0 and s0' registers are offset by one bit; hence, programming the own address register s0' with a value of 55h will result in the value aah being recognized as the PCF8584s slave address (see fig.1). programming of s0' is accomplished via the parallel-bus when a0 is low, with the appropriate bit combinations set in control status register s1 (s1 is written when pin a0 = high). bit combinations for accessing all registers are given in table 5. after reset, s0' has default address 00h (PCF8584 is thus initially in monitor mode, see section 6.12.3). 6.5 clock register s2 register s2 provides control over chip clock frequency and scl clock frequency. s20 and s21 provide a selection of 4 different i 2 c-bus scl frequencies which are shown in table 2. note that these scl frequencies are only obtained when bits s24, s23 and s22 are programmed to the correct input clock frequency (f clk ). table 2 register s2 selection of scl frequency s22, s23 and s24 are used for control of the internal clock prescaler. due to the possibility of varying microcontroller clock signals, the prescaler can be programmed to adapt to 5 different clock rates, thus providing a constant internal clock. this is required to provide a stable time base for the scl generator and the digital filters associated with the i 2 c-bus signals scl and sda. selection for adaption to external clock rates is shown in table 3. bit approximate scl frequency f scl (khz) s21 s20 00 90 01 45 10 11 1 1 1.5 programming of s2 is accomplished via the parallel-bus when a0 = low, with the appropriate bit combinations set in control status register s1 (s1 is written when a0 = high). bit combinations for accessing all registers are given in table 5. table 3 register s2 selection of clock frequency note 1. x = dont care. 6.6 interrupt vector s3 the interrupt vector register provides an 8-bit user-programmable vector for vectored-interrupt microcontrollers. the vector is sent to the bus port (db7 to db0) when an interrupt acknowledge signal is asserted and the eni (enable interrupt) flag is set. default vector values are: vector is 00h in 80xx mode vector is 0fh in 68000 mode. on reset the PCF8584 is in the 80xx mode, thus the default interrupt vector is 00h. 6.7 data shift register/read buffer s0 register s0 acts as serial shift register and read buffer interfacing to the i 2 c-bus. all read and write operations to/from the i 2 c-bus are done via this register. s0 is a combination of a shift register and a data buffer; parallel data is always written to the shift register, and read from the data buffer. i 2 c-bus data is always shifted in or out of shift register s0. internal clock frequency s24 s23 s22 f clk (mhz) 0x (1) x (1) 3 1 0 0 4.43 1016 1108 11112 1997 oct 21 9 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 in receiver mode the data from the shift register is copied to the read buffer during the acknowledge phase. further reception of data is inhibited (scl held low) until the s0 read buffer is read (see section 6.8.1.1). in the transmitter mode data is transmitted to the i 2 c-bus as soon as it is written to the s0 shift register if the serial i/o is enabled (eso = 1). remarks : 1. a minimum of 6 clock cycles must elapse between consecutive parallel-bus accesses to the PCF8584 when the i 2 c-bus controller operates at 8 or 12 mhz. this may be reduced to 3 clock cycles for lower operating frequencies. 2. to start a read operation immediately after a write, it is necessary to read the s0 read buffer in order to invoke reception of the first byte (dummy read of the address). immediately after the acknowledgement, this first byte will be transferred from the shift register to the read buffer. the next read will then transfer the correct value of the first byte to the microcontroller bus (see fig.7). 6.8 control/status register s1 register s1 controls i 2 c-bus operation and provides i 2 c-bus status information. register s1 is accessed by a high signal on register select input a0. for more efficient communication between microcontroller/processor and the i 2 c-bus, register s1 has separate read and write functions for all bit positions (see fig.3). the write-only section provides register access control and control over i 2 c-bus signals, while the read-only section provides i 2 c-bus status information. table 4 control/status register s1 notes 1. for further information see section 6.8.1. 2. for further information see section 6.8.2. 3. logic 1 if not-initialized. control/status bits mode control (1) pin eso es1 es2 eni sta sto ack write only status (2) pin 0 (3) sts ber ad0/lrb aas lab bb read only fig.4 data shift register/bus buffer s0. a ndbook, full pagewidth db7 db6 db5 db4 db3 db2 db1 db0 read buffer data shift register s0 and read buffer shift register read only write only to/from i 2 c-bus sda line to/from microcontroller parallel bus mbe705 1997 oct 21 10 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 6.8.1 r egister s1 control section the write-only section of s1 enables access to registers s0, s0', s1, s2 and s3, and controls i 2 c-bus operation; see table 4. 6.8.1.1 pin (pending interrupt not) when the pin bit is written with a logic 1, all status bits are reset to logic 0. this may serve as a software reset function (see figs 5 to 9). pin is the only bit in s1 which may be both read and written to. pin is mostly used as a status bit for synchronizing serial communication, see section 6.8.2. 6.8.1.2 eso (enable serial output) eso enables or disables the serial i 2 c-bus i/o. when eso is low, register access for initialization is possible. when eso is high, i 2 c-bus communication is enabled; communication with serial shift register s0 is enabled and the s1 bus status bits are made available for reading. table 5 register access control; eso = 0 (serial interface off) and eso = 1 (serial interface on) notes 1. with eso = 0, bits eni, sta, sto and ack of s1 can be read for test purposes. 2. x if eni = 0. 6.8.1.3 es1 and es2 es1 and es2 control selection of other registers for initialization and control of normal operation. after these bits are programmed for access to the desired register (shown in table 5), the register is selected by a logic low level on register select pin a0. 6.8.1.4 eni this bit enables the external interrupt output int, which is generated when the pin bit is active (logic 0). this bit must be set to logic 0 before entering the long-distance mode, and remain at logic 0 during operation in long-distance mode. internal register addressing 2-wire mode a0 es1 es2 iack function eso = 0; serial interface off (see note 1) 10x1 (2) r/w s1: control 000 1 (2) r/w s0': (own address) 001 1 (2) r/w s3: (interrupt vector) 010 1 (2) r/w s2: (clock register) eso = 1; serial interface on 1 0 x 1 w s1: control 1 0 x 1 r s1; status 0001r/w s0: (data) 0011r/w s3: (interrupt vector) x 0 x 0 r s3: (interrupt vector ack cycle)) 1997 oct 21 11 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 6.8.1.5 sta and sto these bits control the generation of the i 2 c-bus start condition and transmission of slave address and r/ w bit, generation of repeated start condition, and generation of the stop condition (see table 7). table 6 register access control; eso = 1 (serial interface on) and es1 = 1; long-distance (4-wire) mode; note 1 note 1. trying to read from or write to registers other than s0 and s1 (setting eso = 0) brings the PCF8584 out of the long-distance mode. table 7 instruction table for serial bus control notes 1. in master receiver mode, the last byte must be terminated with ack bit high (negative acknowledge). 2. if both sta and sto are set high simultaneously in master mode, a stop condition followed by a start condition + address will be generated. this allows chaining of transmissions without relinquishing bus control. 3. all other sta and sto mode combinations not mentioned in table 7 are nops. 6.8.1.6 ack this bit must be set normally to a logic 1. this causes the i 2 c-bus controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). the bit must be reset (to logic 0) when the i 2 c-bus controller is operating in master/receiver mode and requires no further data to be sent from the slave transmitter. this causes a negative acknowledge on the i 2 c-bus, which halts further transmission from the slave device. 6.8.2 r egister s1 status section the read-only section of s1 enables access to i 2 c-bus status information; see table 4. internal register addressing: long-distance (4-wire) mode a0 es1 es2 iack function 1 1 x 1 w s1: control 1 1 x x r s1; status 0 1 x x r/w s0; (data) sta sto present mode function operation 1 0 slv/rec start transmit start + address, remain mst/trm if r/ w=0; go to mst/rec if r/ w=1 1 0 mst/trm repeat start same as for slv/rec 0 1 mst/rec; mst/trm stop read; stop write transmit stop go to slv/rec mode; note 1 1 1 mst data chaining send stop, start and address after last master frame without stop sent; note 2 0 0 any nop no operation; note 3 1997 oct 21 12 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 6.8.2.1 pin bit pending interrupt not (msb of register s1) is a status flag which is used to synchronize serial communication and is set to logic 0 whenever the PCF8584 requires servicing. the pin bit is normally read in polled applications to determine when an i 2 c-bus byte transmission/reception is completed. the pin bit may also be written, see section 6.8.1. each time a serial data transmission is initiated (by setting the sta bit in the same register), the pin bit will be set to logic 1 automatically (inactive). when acting as transmitter, pin is also set to logic 1 (inactive) each time s0 is written. in receiver mode, the pin bit is automatically set to logic 1 (inactive) each time the data register s0 is read. after transmission or reception of one byte on the i 2 c-bus (9 clock pulses, including acknowledge), the pin bit will be automatically reset to logic 0 (active) indicating a complete byte transmission/reception. when the pin bit is subsequently set to logic 1 (inactive), all status bits will be reset to logic 0. pin is also set to zero on a ber (bus error) condition. in polled applications, the pin bit is tested to determine when a serial transmission/reception has been completed. when the eni bit (bit 4 of write-only section of register s1) is also set to logic 1 the hardware interrupt is enabled. in this case, the pin flag also triggers an external interrupt (active low) via the int output each time pin is reset to logic 0 (active). when acting as slave transmitter or slave receiver, while pin = 0, the PCF8584 will suspend i 2 c-bus transmission by holding the scl line low until the pin bit is set to logic 1 (inactive). this prevents further data from being transmitted or received until the current data byte in s0 has been read (when acting as slave receiver) or the next data byte is written to s0 (when acting as slave transmitter). pin bit summary: the pin bit can be used in polled applications to test when a serial transmission has been completed. when the eni bit is also set, the pin flag sets the external interrupt via the int output. setting the sta bit (start bit) will set pin = 1 (inactive). in transmitter mode, after successful transmission of one byte on the i 2 c-bus the pin bit will be automatically reset to logic 0 (active) indicating a complete byte transmission. in transmitter mode, pin is set to logic 1 (inactive) each time register s0 is written. in receiver mode, pin is set to logic 0 (active) on completion of each received byte. subsequently, the scl line will be held low until pin is set to logic 1. in receiver mode, when register s0 is read, pin is set to logic 1 (inactive). in slave receiver mode, an i 2 c-bus stop condition will set pin = 0 (active). pin = 0 if a bus error (ber) occurs. 6.8.2.2 sts when in slave receiver mode, this flag is asserted when an externally generated stop condition is detected (used only in slave receiver mode). 6.8.2.3 ber bus error; a misplaced start or stop condition has been detected. resets bb (to logic 1; inactive), sets pin = 0 (active). 6.8.2.4 lrb/ad0 last received bit or address 0 (general call) bit. this status bit serves a dual function, and is valid only while pin = 0: 1. lrb holds the value of the last received bit over the i 2 c-bus while aas = 0 (not addressed as slave). normally this will be the value of the slave acknowledgement; thus checking for slave acknowledgement is done via testing of the lrb. 2. ad0; when aas = 1 (addressed as slave condition), the i 2 c-bus controller has been addressed as a slave. under this condition, this bit becomes the ad0 bit and will be set to logic 1 if the slave address received was the general call (00h) address, or logic 0 if it was the i 2 c-bus controllers own slave address. 6.8.2.5 aas addressed as slave bit. valid only when pin = 0. when acting as slave receiver, this flag is set when an incoming address over the i 2 c-bus matches the value in own address register s0' (shifted by one bit, see section 6.4), or if the i 2 c-bus general call address (00h) has been received (general call is indicated when ad0 status bit is also set to logic 1, see section 6.8.2.4). 6.8.2.6 lab lost arbitration bit. this bit is set when, in multi-master operation, arbitration is lost to another master on the i 2 c-bus. 1997 oct 21 13 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 6.8.2.7 bb bus busy bit. this is a read-only flag indicating when the i 2 c-bus is in use. a zero indicates that the bus is busy, and access is not possible. this bit is set/reset (logic 1/logic 0) by stop/start conditions. 6.9 multi-master operation to avoid conflict between data and repeated start and stop operations, multi-master systems have some limitations: when powering up multiple PCF8584s in multi-master systems, the possibility exists that one node may power up slightly after another node has already begun an i 2 c-bus transmission; the bus busy condition will thus not have been detected. to avoid this condition, a delay should be introduced in the initialization sequence of each PCF8584 equal to the longest i 2 c-bus transmission, see flowchart PCF8584 initialization (fig.5). 6.10 reset a low level pulse on the reset (clk must run) input forces the i 2 c-bus controller into a well-defined state. all flags in s1 are reset to logic 0, except the pin flag and the bb flag, which are set to logic 1. s0' and s3 are set to 00h. the reset pin is also used for the strobe output signal. both functions are separated on-chip by a digital filter. the reset input signal has to be sufficiently long (minimum 30 clock cycles) to pass through the filter. the strobe output signal is sufficiently short (8 clock cycles) to be blocked by the filter. for more detailed information on the strobe function see section 6.12. 6.11 comparison to the mab8400 i 2 c-bus interface the structure of the PCF8584 is similar to that of the mab8400 series of microcontrollers, but with a modified control structure. access to all i 2 c-bus control and status registers is done via the parallel-bus port in conjunction with register select input a0, and control bits eso, es1 and es2. 6.11.1 d eleted functions the following functions are not available in the PCF8584: always selected (als flag) access to the bit counter (bc0 to bc2) full scl frequency selection (2 bits instead of 5 bits) the non-acknowledge mode (ack flag) asymmetrical clock (asc flag). 6.11.2 added functions the following functions either replace the deleted functions or are completely new: chip clock prescaler assert acknowledge bit (ack flag) register selection bits (es1 and es2 flags) additional status flags (ber, bus error) automatic interface control between 80xx and 68000-type microcontrollers programmable interrupt vector strobe generator bus monitor function long-distance mode [non-i 2 c-bus mode (4-wire); only for communication between parallel-bus processors using the PCF8584 at each interface point]. 6.12 special function modes 6.12.1 s trobe when the i 2 c-bus controller receives its own address (or the 00h general call address) followed immediately by a stop condition (i.e. no further data transmitted after the address), a strobe output signal is generated at the reset/ strobe pin (pin 19). the strobe signal consists of a monostable output pulse (active low), 8 clock cycles long (see fig.9). it is generated after the stop condition is received, preceded by the correct slave address. this output can be used as a bus access controller for multi-master parallel-bus systems. 1997 oct 21 14 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 6.12.2 l ong - distance mode the long-distance mode provides the possibility of longer-distance serial communication between parallel processors via two i 2 c-bus controllers. this mode is selected by setting es1 to logic 1 while the serial interface is enabled (eso = 1). in this mode the i 2 c-bus protocol is transmitted over 4 unidirectional lines, sda out, scl in, sda in and scl in (pins 2, 3, 4 and 5). these communication lines should be connected to line drivers/receivers (example: rs422) for long-distance applications. hardware characteristics for long-distance transmission are then given by the chosen standard. control of data transmission is the same as in normal i 2 c-bus mode. after reading or writing data to shift register s0, long-distance mode must be initialized by setting eso and es1 to logic 1. because the interrupt output int is not available in this operating mode, synchronization of data transmission/reception must be polled via the pin bit. remarks: before entering the long-distance mode, eni must be set to logic 0. when powering up an PCF8584-node in long-distance mode, the PCF8584 must be isolated from the 4-wire bus via 3-state line drivers/receivers until the PCF8584 is properly initialized for long-distance mode. failure to implement this precaution will result in system malfunction. 6.12.3 m onitor mode when the 7-bit own address register s0' is loaded with all zeros, the i 2 c-bus controller acts as a passive i 2 c monitor. the main features of the monitor mode are: the controller is always selected. the controller is always in the slave receiver mode. the controller never generates an acknowledge. the controller never generates an interrupt request. a pending interrupt condition does not force scl low. bb is set to logic 0 after detection of a start condition, and reset to logic 1 after a stop condition. received data is automatically transferred to the read buffer. bus traffic is monitored by the pin bit, which is reset to logic 0 after the acknowledge bit of an incoming byte has been received, and is set to logic 1 as soon as the first bit of the next incoming byte is detected. reading the data buffer s0 sets the pin bit to logic 1. data in the read buffer is valid from pin = 0 and during the next 8 clock pulses (until next acknowledge). aas is set to logic 1 at every start condition, and reset at every 9th clock pulse. 7 software flowchart examples 7.1 initialization the flowchart of fig.5 gives an example of a proper initialization sequence of the PCF8584. 7.2 implementation the flowcharts (figs 6 to 9) illustrate proper programming sequences for implementing master transmitter, master receive, and master transmitter, repeated start and master receiver modes in polled applications. 1997 oct 21 15 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.5 PCF8584 initialization sequence. handbook, full pagewidth start a0 = high a0 = low reset minimum 30 clock cycles delay: wait a time equal to the longest i 2 c message to synchronize bb-bit. (multimaster systems only send byte 80h send byte 55h PCF8584 resets to slave receiver mode parallel bus interface determined by PCF8584 (80xx/68xxx) initialization of PCF8584 completed send byte a0h send byte 1ch send byte c1h end address line a0 power-on a0 = high a0 = low a0 = high a0 = high enables data transfer to/from register s1 a0 = low access to all other registers defined by the bit pattern in register s1 loads byte 80h into register s1' i.e. next byte will be loaded into register s0' (own address register); serial interface off. loads byte 55h into register s0'; effective own address becomes aah. loads byte a0h into register s1, i.e. next byte will be loaded into the clock control register s2. loads byte 1ch into register s2; system clock is 12 mhz; scl = 90 khz. loads byte c1h into register s1; register enable serial interface, set i 2 c-bus into idle mode; sda and scl are high. the next write or read operation will be to/from data transfer register s0 if a0 = low. on power-on, if an PCF8584 node is powered-up slightly after another node has already begun an i 2 c-bus transmission, the bus busy condition will not have been detected. thus, introducing this delay will insure that this condition will not occur. mbe714 1997 oct 21 16 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.6 PCF8584 master transmitter mode. h andbook, full pagewidth start read byte from s1 register end a0 = high is bus busy? (bb = 0?) yes no pin bit = 0? no yes slave acknowledged? (lrb = 0?) yes send byte 'slave address' a0 = low send c5h to control register s1 load 'slave address' into s0 register: 'slave address' = value of slave address (7-bits + r/w = 0). after reset, default = '0' n = 0 (data byte counter); m = number of data bytes to be transferred read byte from s1 register n = m no n = n + 1 send byte 'data' yes a0 = high PCF8584 remains in master transmitter mode if r/w bit of 'slave address' = 0 a0 = high a0 = low load 'data' into bus buffer register s0; data is transmitted. send byte c3h transmission completed a0 = high load c3 into the s1 control register: PCF8584 generates 'stop' condition. PCF8584 goes into slave receiver mode load c5h into s1. 'c5h' = PCF8584 generates the 'start' condition and clocks out the slave address and the clock pulse for slave acknowledgement. next byte(s) sent to the s0 register will be immediately transferred over the i 2 c-bus. poll for transmission finished. mbe715 1997 oct 21 17 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.7 PCF8584 master receiver mode. (1) the first read of the s0 register is a dummy read of the slave address which should be discarded. the first read of the s0 register simultaneously reads the current value of s0 and then transfers the first valid data byte from the i 2 c-bus to s0. handbook, full pagewidth a0 = low load 'slave address' into s0 register: 'slave address' = 7 bits + r/w = 1. is the i 2 c-bus busy? PCF8584 generates 'start' condition, sends out slave address + rd to i 2 c-bus and generates 9th clock pulse for slave ack. set-up software counters. set ack bit s1 to 0 in preparation for negative acknowledgement. PCF8584 generates 'stop' condition. PCF8584 goes into slave receiver mode. this command transfers the final data byte from the data buffer to accumulator. because the stop condition was previously executed, no i 2 c-bus activity takes place. this command simultaneously receives the final data byte from the i 2 c-bus and loads it into register s0. neg. ack is also sent. is bus busy? (bb = 0?) start end send byte 'slave address' to s0 a0 = high read byte from s1 status register a0 = high send byte c5h to s1 control register a0 = high read byte from s1 status register a0 = low read data byte from s0 register (1) n = n + 1 n = 0 (data byte counter) m = number of data bytes to be read yes no a0 = high send byte 40h to control register s1 a0 = low read data byte from s0 register (1) a0 = high read byte from s1 status register a0 = high send byte c3h to s1 a0 = low read final data byte from s0 register pin = 0? no yes slave ack? (lrb = 0?) n = m - 1? yes no no (an error has occured) pin = 0? yes mgl009 1997 oct 21 18 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.8 master transmitter followed by repeated start and becoming master receiver. n dbook, full pagewidth start i 2 c-bus write routine (master transmitter mode excluding final stop) send byte 45h send byte 'slave address' i 2 c-bus read routine (master receiver mode) end PCF8584 configured as master transmitter PCF8584 configured as master receiver a0 = high a0 = low load 45h into the s1 register; PCF8584 generates the repeated 'start condition' only. the current contents of register s0 is not clocked out onto the i 2 c-bus. the next byte sent to register s0 should be the 'slave address' + read bit. load 'slave address' into the s0 register. once loaded, it is automatically clocked out over the i 2 c-bus. 'slave address' = slave address (7 bits) + r/w bit set '1'. mbe712 1997 oct 21 19 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.9 slave receiver/slave transmitter modes. handbook, full pagewidth start read byte from s1 register end tx a0 = high a0 = low addressed as slave (aas = 1?) no yes read byte from s1 register pin bit = 0? yes no read byte from s0 register read or write? (lsb = 1 or 0?) read byte from s1 register pin bit = 0? r/w = 1 slave transmitter mode no yes negative ack received? (lrb = 1?) yes no write last data byte to s0 register a0 = high a0 = low end rx read byte from s1 register pin bit = 0? r/w = 0 slave receiver mode no yes stop detected? (sts = 1?) yes no read last data byte from s0 register write data to s0 register read data from s0 register pin deactivated (set to '1') PCF8584 goes into slave receiver mode read incoming address to determine if the r/w bit is 0 or 1 this will differentiate between slave receiver or slave transmitter modes. check that 'own address' has arrived correctly check whether 'addressed as slave' mbe713 1997 oct 21 20 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 8i 2 c-bus timing diagrams the diagrams (figs 10 to 13) illustrate typical timing diagrams for the PCF8584 in master/slave functions. for detailed description of the i 2 c-bus protocol, please refer to the i 2 c-bus and how to use it ; philips document ordering number 9398 393 40011. fig.10 bus timing diagram; master transmitter mode. handbook, full pagewidth mbe709 stop condition interrupt ack nbyte ack interrupt first-byte (e4h) interrupt r/w = 0 ack 7-bit address (76h) start condition from slave receiver sda scl int master PCF8584 writes data to slave transmitter. fig.11 bus timing diagram; master receiver mode. handbook, full pagewidth mbe710 stop condition no ack nbyte ack interrupt first-byte (discard) interrupt r/w = 1 ack 7-bit address (76h) start condition from slave sda scl int 'dummy read' must be executed here from master receiver master PCF8584 reads data from slave transmitter. 1997 oct 21 21 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.12 bus timing diagram; slave transmitter mode. handbook, full pagewidth mbe711 stop condition no ack nbyte ack interrupt first-byte: 1fh interrupt r/w = 1 ack 7-bit address (0ch) start condition from slave PCF8584 sda scl int from master receiver interrupt external master receiver reads data from PCF8584. fig.13 bus timing diagram; slave receiver mode. handbook, full pagewidth mbe708 interrupt (after stop) stop condition interrupt ack nbyte ack interrupt first-byte (cch) interrupt r/w = 0 ack 7-bit address (62h) start condition from slave PCF8584 sda scl int slave PCF8584 is written to by external master transmitter. 1997 oct 21 22 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 9 limiting values in accordance with the absolute maximum rating system (iec 134). 10 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is good practice to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter min. max. unit v dd supply voltage - 0.3 +7.0 v v i voltage range (any input) - 0.8 v dd + 0.5 v i i dc input current (any input) - 10 +10 ma i o dc output current (any output) - 10 +10 ma p tot total power dissipation - 300 mw p o power dissipation per output - 50 mw t amb operating ambient temperature - 40 +85 c t stg storage temperature - 65 +150 c 1997 oct 21 23 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 11 dc characteristics v dd =5v 10%; t amb = - 40 to +85 c; unless otherwise speci?ed. notes 1. test conditions: 22 k w pull-up resistors on d0 to d7; 10 k w pull-up resistors on sda, scl, rd; reset connected to v ss ; remaining pins open-circuit. 2. clk waveform of 12 mhz with 50% duty factor. 3. clk, iack, a0, cs, wr, rd, reset and d0 to d7 are ttl level inputs. 4. sda and scl are cmos level inputs. 5. clk, iack, a0, cs and wr. 6. d0 to d7. 7. dtack, strobe. 8. d0 to d7 3-state, sda, scl, int, rd, reset. symbol parameter conditions min. typ. max. unit supply v dd supply voltage 4.5 5.0 5.5 v i dd supply current standby; note 1 -- 2.5 m a operating; notes 1 and 2 -- 1.5 ma inputs clk, iack, a0, cs, wr, rd, reset and d0 to d7 v il low level input voltage note 3 0 - 0.8 v v ih high level input voltage note 3 2.0 - v dd v sda and scl v il low level input voltage note 4 0 - 0.3v dd v v ih high level input voltage note 4 0.7v dd - v dd v r i resistance to v dd t amb =25 c; note 5 25 - 100 k w outputs i oh high level output current v oh = 2.4 v; note 6 and 7 - 2.4 -- ma i ol low level output current v ol = 0.4 v; note 6 3.0 -- ma i ol leakage current note 8 - 1 - +1 m a 1997 oct 21 24 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 12 i 2 c-bus timing specifications all the timing limits are valid within the operating supply voltage and ambient temperature range; v dd =5v 10%; t amb = - 40 to +85 c; and refer to v il and v ih with an input voltage of v ss to v dd. 13 parallel interface timing all the timing limits are valid within the operating supply voltage and ambient temperature range: v dd =5v 10%; t amb = - 40 to +85 c; and refer to v il and v ih with an input voltage of v ss to v dd . c l = 100 pf; r l = 1.5 k w (connected to v dd ) for open-drain and high-impedance outputs, where applicable (for measurement purposes only). symbol parameter min. typ. max. unit f scl scl clock frequency -- 100 khz t sw tolerable spike width on bus -- 100 ns t buf bus free time 4.7 --m s t su;sta start condition set-up time 4.7 --m s t hd;sta start condition hold time 4.0 --m s t low scl low time 4.7 --m s t high scl high time 4.0 --m s t r scl and sda rise time -- 1.0 m s t f scl and sda fall time -- 0.3 m s t su;dat data set-up time 250 -- ns t hd;dat data hold time 0 -- ns t vd;dat scl low to data out valid -- 3.4 m s t su;sto stop condition set-up time 4.0 --m s symbol parameter conditions min. typ. max. unit t r clock rise time see fig.14 -- 6ns t f clock fall time see fig.14 -- 6ns t clk input clock period (50% 5% duty factor) see fig.14 83 - 333 ns t clrl cs set-up to rd low see fig.16 and note 1 20 -- ns t clwl cs set-up to wr low see fig.15 and note 1 20 -- ns t rhch cs hold from rd high see fig.16 0 -- ns t whch cs hold from wr high see fig.15 0 -- ns t avwl a0 set-up to wr low see fig.15 10 -- ns t avrl a0 set-up to rd low see fig.16 10 -- ns t whai a0 hold from wr high see fig.15 20 -- ns t rhai a0 hold from rd high see fig.16 10 -- ns t wlwh wr pulse width see fig.15 230 - 1000 ns t rlrh rd pulse width see fig.16 230 - 1000 ns t dvwh data set-up before wr high see fig.15 150 -- ns t rldv data valid after rd low see fig.16 - 160 180 ns t whdi data hold after wr high see fig.15 20 -- ns t rhdf data bus ?oating after rd high see fig.16 -- 150 ns 1997 oct 21 25 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 notes 1. a minimum of 6 clock cycles must elapse between consecutive parallel-bus accesses when the i 2 c-bus controller operates at 8 or 12 mhz. this may be reduced to 3 clock cycles for lower operating frequencies. 2. not for s1. t avcl a0 set-up to cs low see figs 17 and 18 10 -- ns t wlcl r/ wr set-up to cs low see fig.17 10 -- ns t rhcl r/wr set-up to cs low see fig.18 10 -- ns t cldv data valid after cs low see fig.18 and note 2 - 160 180 ns t cldl dt ack low after cs low see figs 17 and 18 - 2t clk +75 3t clk + 150 ns t chai a0 hold from cs high see fig.18 0 -- ns t chrl r/ wr hold from cs high see fig.18 0 -- ns t chwh r/wr hold from cs high see fig.17 0 -- ns t chdf data bus ?oat after cs high see fig.18 -- 150 ns t chde dt ack high from cs high see figs 17 and 18 - 100 120 ns t chdi data hold after cs high see fig.17 0 -- ns t dvcl data set-up to cs low see fig.17 0 -- ns t alie int high from iack low see figs 19 and 20 - 130 180 ns t aldv data valid after iack low see figs 19 and 20 - 200 250 ns t alae iack pulse width see fig.20 230 -- ns t ahdi data hold after iack high see fig.20 -- 30 ns t aldl dt ack low from iack low see fig.20 - 2t clk +75 3t clk + 150 ns t ahde dt ack high from iack high see fig.20 - 120 140 ns t w4 reset pulse width see fig.21 30t clk -- ns t w5 strobe pulse width see fig.22 8t clk 8t clk +90 - ns t clcl cs low see figs 17 and 18 - t cldl +t chde - ns symbol parameter conditions min. typ. max. unit 1997 oct 21 26 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.14 clock input timing. handbook, full pagewidth t clk 35.5 ns min 6 ns max 6 ns max clk t r t f t f 35.5 ns min mla013 - 1 fig.15 bus timing (80xx mode); write cycle. t wlwh t avwl t whai t clwl t whch a0 cs wr d0 to d7 mla014 - 1 t dvwh t whdi data valid 1997 oct 21 27 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.16 bus timing (80xx mode); read cycle. handbook, full pagewidth t rlrh t avrl t rhai t clrl t rhch a0 cs rd d0 to d7 mla015 - 1 t rhdf t rldv data valid fig.17 bus timing (68000 mode); write cycle. handbook, full pagewidth mla017 - 1 a0 d0 to d7 data valid t chai t avcl t wlcl t clcl t chwh t dvcl t chdi t cldl t chde r/w cs dtack 1997 oct 21 28 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.18 bus timing (68000 mode); read cycle. mla016 - 1 a0 d0 to d7 data valid t chal t avcl t rhcl t clcl t chrl t cldv t chdf t cldl t chde r/w cs dtack fig.19 interrupt timing (80xx mode). t alie t alae t aldv t ahdi data valid d0 to d7 iack int mla018 - 1 1997 oct 21 29 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.20 interrupt timing (68000 mode). handbook, full pagewidth t alie t alae t aldl t ahdi t aldv t ahde data valid d0 to d7 iack dtack int mla019 - 1 fig.21 reset timing. t w4 clk reset mla020 - 1 1997 oct 21 30 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.22 strobe timing. clk t w5 strobe mla021 - 1 1997 oct 21 31 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 14 application information fig.23 application diagram using the 8048/8051. data wr int rd scl sda cs a0 ale 8048/8051 PCF8584 address bus decoder mbe704 1997 oct 21 32 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.24 application diagram using the 68000. as uds lds decoder address interrupt handler data dtack r/w scl sda cs a1 a1, a2, a3 iack int fcx ipx 68000 PCF8584 mbe702 1997 oct 21 33 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 fig.25 application diagram using the 8088. data iow ior iack intr int scl sda cs a0 ale 8088 PCF8584 address bus decoder mbe703 1997 oct 21 34 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 14.1 application notes additional application notes are available from philips semiconductors: 1. an95068: c routines for the PCF8584. 2. an96040: using the PCF8584 with non-specified timings and other frequently asked questions . 3. an90001: interfacing PCF8584 i 2 c-bus controller to 80(c)51 family of microcontrollers . fig.26 PCF8584 diode protection. maximum forward current: 5 ma; maximum reverse voltage: 5 v. handbook, full pagewidth mbe701 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 substrate reset/strobe wr (r/w) cs rd (dtack) db7 db6 db5 db4 db3 v dd sda or sda out scl or scl in iack or sda in int or scl out a0 db0 db1 db2 v ss clk (1) 1997 oct 21 35 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 15 package outlines unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot146-1 92-11-17 95-05-24 a min. a max. b z max. w m e e 1 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 6.40 6.22 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 2.0 4.2 0.51 3.2 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 0.25 0.24 0.14 0.12 0.01 0.10 0.30 0.32 0.31 0.39 0.33 0.078 0.17 0.020 0.13 sc603 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 20 1 11 10 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) (1) dip20: plastic dual in-line package; 20 leads (300 mil) sot146-1 1997 oct 21 36 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013ac pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.050 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x q a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 95-01-24 97-05-22 1997 oct 21 37 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 16 soldering 16.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 16.2 dip 16.2.1 s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 16.2.2 r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 16.3 so 16.3.1 r eflow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 16.3.2 w ave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.3.3 r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 1997 oct 21 38 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 17 definitions 18 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 19 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 1997 oct 21 39 philips semiconductors product speci?cation i 2 c-bus controller PCF8584 notes internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca55 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 417067/00/04/pp40 date of release: 1997 oct 21 document order number: 9397 750 02932 |
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